Resilient Routing Implementation in 2D Mesh NoC

With the rapid shrinking of technology and growing integration capacity, the probability of failures in Networks-on-Chip (NoCs) increases and thus, fault tolerance is essential. Moreover, the unpredictable locations of these failures may influence the regularity of the underlying topology, and a regular 2D mesh is likely to become irregular. Thus, for these failure-prone networks, a viable routing framework should comprise a topology-agnostic routing algorithm along with a cost-effective, scalable routing mechanism able to handle failures, irrespective of any particular failure patterns. Existing routing techniques designed to route irregular topologies efficiently lack flexibility (logic-based), scalability (table-based) or relaxed switch design (uLBDR-based). Designing an efficient routing implementation technique to address irregular topologies remains a pressing research problem. To address this, we present a fault resilient routing mechanism for irregular 2D meshes resulting from failures. To handle irregularities, it avoids using routing tables and employs a few fixed configuration bits per switch resulting in a scalable approach. Experiments demonstrate that the proposed approach is guaranteed to tolerate all locations of single and double-link failures and most multiple failures. Also, unlike uLBDR it is not restricted to any particular switching technique and does not replicate any extra messages. Along with fault tolerance, the proposed mechanism can achieve better network performance in fault-free cases. The proposed technique achieves graceful performance degradation during failure. Compared to uLBDR, our method has 14% less area requirements and 16% less overall power consumption

A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs"

© ACM, 2015. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in ACM Transactions on Embedded Computing Systems, Vol. 14, No. 1, Article 2, january 2015. http://doi.acm.org/10.1145/2668121[EN] In the Ghiribaldi et al. [2013] paper, a complete self-testing and self configuring NoC infrastructure for cost-effective MPSoCs was presented in order to make NoC architecture tolerant to faults. To overcome the complexity involved during the complete reconfiguration of routing instances in the face of most of the usual failure patterns, Ghiribaldi et al. [2013] proposed a fast self-reconfiguration algorithm. The algorithm is based on segment-based routing implemented using Logic-Based Distributed Routing (LBDR) and claimed to have handled the most common NoC faults. The purpose of this comment is to demonstrate the inconsistency of the fast self-configuration method presented in Ghiribaldi et al. [2013]. To handle inconsistency, we present the correct set of LBDR bits and also argue that complete reconfiguration of the routing instance is mandatory to handle some fault combinations. New coverage results of the fast self-reconfiguration algorithm of Ghiribaldi et al. [2013] are also presented.This work is supported by Indo-Spain DST project under grant DST/INT/Spain/P35/11/1 and Spanish Ministerio de Economa y Competitividad (MINECO) under grant PRI-PIBIN-2011-0989Bishnoi, R.; Laxmi, V.; Gaur, MS.; Flich Cardo, J.; Trivino, F. (2015). A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs". ACM Transactions in Embedded Computing Systems. 14(1):1-9. https://doi.org/10.1145/2668121S19141A. Ghiribaldi, D. Ludovici, F. Triviño, A. Strano, J. Flich, J. L. Sánchez, F. Alfaro, M. Favalli, and D. Bertozzi. 2013. A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. 12, 4 (July 2013), 106:1--106:29. DOI: http://dx.doi.org/10.1145/2485984.2485994A. Mejia. 2008. Design and Implementation of Efficient Topology Agnostic Routing Algorithms for Interconnection Networks. Ph.D. Dissertation. University of Valencia.A. Mejia, J. Flich, and J. Duato. 2008. On the potentials of segment-based routing for NoCs. In Proceedings of the 37th International Conference on Parallel Processing (ICPP’08). IEEE, 594--603. DOI: http://dx.doi.org/10.1109/ICPP.2008.56S. Rodrigo, S. Medardoni, J. Flich, D. Bertozzi, and J. Duato. 2009. Efficient implementation of distributed routing algorithms for NoCs. IET Comput. Digital Techn. 3, 5 (2009), 460--475. DOI: http://dx.doi.org/10.1049/iet-cdt.2008.0092A. Strano, D. Bertozzi, F. Trivino, J. L. Sanchez, F. J. Alfaro, and J. Flich. 2012. OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. In Proceedings of the International Conference on Embedded Computer Systems (SAMOS’12). 86--95. DOI: http://dx.doi.org/10.1109/SAMOS.2012.640416

Hybrid fault tolerant routing algorithm in NoC

Network-on-Chip has been a growing design paradigm with the rise in Multi-Processor System on Chip (MPSoCs) primarily due to its scalability. While regular meshes (2 or 3-dimensional) are the usual proposal for such a paradigm, a real chip may not follow it. Heterogeneous cores, hardware failures or manufacturing defects can possibly cause irregular topologies in a Network-on-Chip. Selection of a routing algorithm is an important challenge in NoC design as it affects power consumption, communication latency and overall system performance. Routing can be supported in such faulty environment by use of routing tables. But this is not a scalable solution as table size grows with network size. Logic Based Distributed Routing (LBDR) is proposed as a new routing implementation technique which offers compact routing implementation and fault tolerance without use of routing table. In this paper we propose a Hybrid Fault Tolerant Routing Algorithm (HFTRA), which aims to provide fault tolerance support in presence of on-chip link failures. Proposed routing is implemented with LBDR scheme. Analysis of the method has shown the effectiveness of proposed scheme as compared to routing tables when implemented using LBDR

Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs

Network-on-Chip (NoC) is one of the promising communication architecture to provide scalability for many core designs. However, deep sub-micron technology related effects impact NoC reliability. Hence under this condition NoC must continue to provide at-least a path between each pair of its components as long as path is available. In this paper we propose fault tolerant routing implementation solution, targeting the implementation of any distributed routing algorithm for regular as well as irregular 2D meshes generated due to failures. The proposed approach is logic based and does not use any routing table to implement a routing algorithm. Experimental results show that proposed method provides 14% reduction in area when compared with existing logic based on-chip fault tolerant implementations. Further, proposed approach degrades performance gracefully while preserving 100% coverage to all irregular topologies generated from 2D mesh.</p

σ n LBDR: generic congestion handling routing implementation for two-dimensional mesh network-on-chip

The number of cores on a chip is increasing from a few cores to thousands. However, the communication mechanisms for these systems do not scale at the same pace, leading to certain challenges. One of them is on-chip congestion. There are many table-based approaches for congestion handling and avoidance, but these are not acceptable as they impose high area and power overheads. In this study, the authors propose two congestion handling strategies aiming to capture the congestion in few bits to avoid congested routes. The first approach called σ n LBDR (logic based distributed routing) captures congestion present at nodes n-hop away from the current node, reducing area, power and overall packet latency. However, all nodes in the network do not experience same congestion level. For this, their second approach, weighted σ n LBDR, uses a different set of bits for each node and results in the further improvement in area and power. This study shows a comparison of both approaches with each other and also with other similar approaches. From their experimental results, they show that σ n LBDR and weighted σ n LBDR improve latency by 20 and 30%, respectively, and have less area and power overhead as compared with baseline table-based approach

CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip

To deal with the communication challenges of current and future many-core architectures, Network-on-Chip (NoC) has been proposed as a promising alternative. Regular 2D mesh topology is the most preferred design choice for NoCs. Hardware failures owing to manufacturing, wear-out, aging etc., however, may disrupt the regularity of 2D mesh. Sustaining routing under these circumstances becomes a challenge. Though traditional table based routing method is flexible enough to handle any irregularity, it is neither scalable nor cost-effective solution. Scalable distributed logic based solutions like uLBDR have limited flexibility and work only in restricted architectural space despite complex switch design. To overcome these limitations, this paper presents CERI (Cost-Effective Routing Implementation), an efficient logic based routing capable of handling failure-induced irregularities in 2D mesh. Implementation of proposed approach does not require tables or a complex switch design. Performance analysis of CERI demonstrates its cost effectiveness as area and power requirements are reduced respectively by (14%) and (16%) than previously proposed logic based solution uLBDR.</p